Vero layout of the ISP decimator noise gate. This one is based on a “true-bypass” version of the schematic foregoing the IC switching, buffered bypass and whatnot. I’ve yet to verify this (as usual) but it looks interesting enough that I’ll give this one a try soon. Let me know if you beat me to it.
Update (30.12.2011): Just finished building this circuit and it works.
Update (06.08.2012): I really wanted to fit this in a 1590B, but given the size of the vero that wasn’t going to happen any time soon. I went with the next size, the 125B, which was still just barely able to house the board. Placing it component-side down was the only way it would work and that’s why the insides are as disappointing as they are. Love the effect, though!